This application claims the priority benefit of Taiwan application serial no. 88116997, filed Oct. 2, 1999.
1. Field of the Invention
The present invention relates to a fabrication method for a multilevel metal interconnect (MLM). More particularly, the present invention relates to a dual damascene manufacturing process.
2. Description of the Related Art
Currently, semiconductor manufacturing has entered the stage of deep sub-micron manufacturing in which the device dimensions are being reduced dramatically. A reduction of the device dimensions then causes an increase in the RC time delay. In order to mitigate the RC time delay problem and to accommodate the demand for a high operational speed of electronic devices, various types of material have been employed for the manufacturing of the metal line and the inter-metal dielectrics (IMD) to increase the reliability and the speed of the devices.
By the backend of the manufacturing of a semiconductor device, the width of the metal line has been gradually decreased and correspondingly, the current density to be supported by the metal line slowly increases. As a result, the metal line, which is conventionally formed with aluminum, is easily affected by electron migration (EM), leading to a reduction of device reliability.
In order to resolve the problem mentioned in the above, copper, which has a lower resistance and a low electron migration effect, has been chosen for use in the manufacturing of the metal line of a semiconductor device.
Copper, however, is not easily etched with the common etchants. The conventional approach, for example, drying etching the metal, cannot be used when manufacturing a copper metal line. A dual damascene manufacturing process is thus used, instead.
FIGS. 1A to 1E are schematic, cross-sectional views showing the dual damascene manufacturing process according to the prior art.
Referring to FIG. 1A, a silicon oxide layer 102 is formed covering a substrate 100, followed by forming a silicon nitride layer 104 to cover the silicon oxide layer 102. Another silicon oxide layer 106 is further formed to cover the silicon nitride layer 104. The silicon oxide layer 102, the silicon nitride layer 104 and the silicon oxide layer 106, formed by, for example, plasma enhanced chemical vapor deposition (PECVD), serve as the inter-metal dielectrics.
As shown in FIG. 1B, photolithography and etching are further conducted to form a trench line 108 in the silicon oxide layer 106. During the definition of the trench line 108, the silicon nitride layer 104 serves as an etching stop layer, preventing an over-etching from occurring during the formation of the trench line 108.
Referring to FIG. 1C, photolithography and etching are further conducted to define the silicon nitride layer 104 and the silicon oxide layer 102 to form a via 110 under the trench line 108.
Continuing to FIG. 1D, a barrier layer 112 and a copper layer 114 are sequentially formed to fill the trench line 108 and the via 110 and to cover the silicon oxide layer 106. The barrier layer 112 is, for example, titanium nitride (TiN). The barrier layer 112 and the copper layer 114 are formed by, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD).
As shown in FIG. 1E portions of the barrier layer 112 (FIG. 1D) and the copper layer 114 (FIG. 1D), which are covering the surface of the silicon oxide layer 106, are removed, leaving the barrier layer 112a and the copper layer 114a in the trench line 108 and in the via 110. The barrier layer 112 and the copper layer 114 are removed by, for example, chemical mechanical polishing (CMP).
The profiles of the trench line 108 and the via 110 formed according to the above manufacturing process, however, are sharp. The issue of a high aspect ratio (AR) becomes even more significant when the dimensions of a semiconductor device are reduced. A good conformity with the subsequently formed barrier layer and copper layer is thus difficult to achieve. Furthermore, voids and seams are easily formed in the center of the copper layer 114 in the via 110, leading to a decrease of the reliability of the metal interconnect.
Based on the foregoing, a dual damascene manufacturing process is provided, in which a larger and smoother opening is formed at the top part of the via to prevent the problem of voids and seams which are being formed in the via and the trench line.
Accordingly, the current invention provides a dual damascene manufacturing process, which is applicable to a dual damascene structure. The dual damascene structure is formed by forming sequentially a first dielectric layer with a spin-on-glass approach, an etching stop layer and a thermally stable second dielectric layer on a substrate, wherein a via is formed in the first dielectric layer and a trench line is formed in the second dielectric layer. The via is located under the trench line, and the etching stop layer at the bottom of the trench line is removed. Thereafter, a thermal treatment is conducted to smooth the surface of the first dielectric layer at the bottom of the trench line and in the via to result in a larger and a smoother opening at the top part of the via. A barrier layer is then formed, covering the second dielectric layer, the trench line and the via, followed by forming a metal layer to cover the barrier layer, and to fill the trench line and the via. Subsequently, the barrier layer and the metal layer on the surface of the second dielectric layer are removed.
The fabrication of the dual damascene structure according to the present invention further includes providing a substrate using a spin-on-glass method to form a first dielectric layer to cover the substrate, followed by forming an etching stop layer to cover the first dielectric layer. A first photolithography and etching is conducted to define the etching stop layer and to form an opening, wherein the opening is used to define the position of the subsequently formed via. Thereafter, a thermally stable second dielectric layer is formed, covering the etching stop layer and the opening. A second photolithography and etching is conducted to define the second dielectric layer and to form a trench line in the second dielectric layer. Concurrently, using the etching stop layer as an etching mask, a via is formed in the first dielectric layer through the opening, such that the via is located under the trench line. The etching stop layer at the bottom of the trench line is then removed. After the formation of the dual damascene structure, a thermal treatment is then conducted to smooth the surface of the first dielectric layer at the bottom of the trench line and in the via to form a larger and smoother opening on the top part of the via. A barrier layer and a metal layer are further formed to fill the trench line and the via, wherein the barrier layer and the metal layer on the second dielectric layer are thus subsequently removed
The via formed according to the present version of the invention comprises a larger and smoother opening even though the dimensions of the via are further being reduced to accommodate the current design rule of the manufacturing of a semiconductor device. The subsequently formed barrier layer and metal layer, as a result, have a good conformity with the underlying structure.
A high aspect ratio due to the reduction of the dimensions of the via as seen in the conventional practice would lead to the formation of voids and seams in the center of the via, causing the reliability of the metal interconnect to decrease. The via formed according to the present version of the invention, in contrast, comprises a larger and a smoother opening at the top part of the via, the problem associated with the formation of voids and seams in the via is thus avoided. Without the presence of voids and seams, the reliability of the metal interconnect is thus increased.
Furthermore, the quality of the barrier layer and the metal layer formed by physical vapor deposition is better than that formed by chemical vapor deposition, and the cost for a physical vapor deposition process is lower. The step coverage capability of physical vapor deposition, however, is inferior. Since the opening formed on the top part of the via of the present invention comprises a larger and smoother opening, the step coverage capability of physical vapor deposition is improved when the barrier layer and metal layer are formed. The barrier layer and the metal layer are thereby formed with a better film characteristic, a lower cost, and a better step coverage capability.
Generally speaking, the present invention provides a more flexible design rule and a more simplified manufacturing process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.